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Integrated Circuit Systems, Inc.
ICS952004
Programmable Timing Control HubTM for P4TM processor
Recommended Application: SIS 645/650 style chipsets. Output Features: * 2 - Pairs of differential CPUCLKs (differential current mode) * 1 - SDRAM @ 3.3V * 8 - PCI @3.3V * 2 - AGP @ 3.3V * 2 - ZCLKs @ 3.3V * 1- 48MHz, @3.3V fixed. * 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz) * 3- REF @3.3V, 14.318MHz. Features/Benefits: * Selectable asynchronous/synchronous AGP, ZCLK and PCI outputs * Programmable output frequency, divider ratios, output rise/ falltime, output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * For PC133 SDRAM system use the ICS9179-16 as the memory buffer. * For DDR SDRAM system use the ICS93705 or ICS93722 as the memory buffer. * Uses external 14.318MHz crystal. Key Specifications: * PCI - PCI output skew: < 500ps * CPU - SDRAM output skew: < 1ns * AGP - AGP output skew: <150ps
Pin Configuration
VDDREF **FS0/REF0 **FS1/REF1 **FS2/REF2 GNDREF X1 X2 GNDZ ZCLK0 ZCLK1 VDDZ *PCI_STOP# VDDPCI **FS3/PCICLK_F0 **FS4/PCICLK_F1 PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDSD SDRAM GNDSD CPU_STOP#* CPUCLKT_1 CPUCLKC_1 VDDCPU GNDCPU CPUCLKT_0 CPUCLKC_0 IREF GNDA VDDA SCLK SDATA PD#*/Vtt_PWRGD GNDAGP AGPCLK0 AGPCLK1 VDDAGP VDDA48 48MHz 24_48MHz/MULTISEL* GND48
48-Pin 300-mil SSOP
* These inputs have a 120K pull up to VDD. ** These inputs have a 120K pull down to GND.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
ICS952004
2
REF (1:0)
CPU DIVDER
Stop
2 2
CPUCLKT (1:0) CPUCLKC (1:0)
Functionality
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 CPU SDRAM ZCLK (MHz) 66.67 66.67 66.67 66.67 60.00 62.50 66.67 80.00 66.67 62.50 71.43 66.67 66.67 63.33 63.33 50.00 AGP (MHz) 66.67 66.67 66.67 66.67 60.00 62.50 66.67 66.67 66.67 62.50 83.33 66.67 66.67 63.33 63.33 50.00 PCI (MHz) 33.33 33.33 33.33 33.33 30.00 31.25 33.33 33.33 33.33 31.25 41.67 33.33 33.33 31.67 31.67 25.00 FS4 FS3 FS2 FS1 FS0 (MHz) (MHz) 0 0 0 0 0 66.67 66.67 0 0 0 0 1 100.00 100.00 0 0 0 1 0 100.00 200.00 0 0 0 1 1 100.00 133.33 0 0 1 0 0 100.00 150.00 0 0 1 0 1 100.00 125.00 0 0 1 1 0 100.00 160.00 0 0 1 1 1 100.00 133.33 0 1 0 0 0 100.00 200.00 0 1 0 0 1 100.00 166.67 0 1 0 1 0 100.00 166.67 0 1 0 1 1 80.00 133.33 0 1 1 0 0 80.00 133.33 0 1 1 0 1 95.00 95.00 0 1 1 1 0 95.00 126.67 0 1 1 1 1 66.67 66.67
SDATA SCLK FS (4:0) PD# PCI_STOP# CPU_STOP# MULTISEL PD#/Vtt_PWRGD
Control Logic
ZCLK DIVDER
ZCLK (1:0)
2
PCI DIVDER
Stop
6
PCICLK (9:0) PCICLK_F (1:0)
2
AGP DIVDER
2
AGP (1:0)
Config. Reg.
SDRAM DIVDER
SDRAM I REF
Power Groups
VDDCPU = CPU VDDPCI = PCICLK_F, PCICLK VDDSD = SDRAM AVDD48 = 48MHz, 24MHz, fixed PLL AVDD = Analog Core PLL VDDAGP= AGP VDDREF = Xtal, REF VDDZ = ZCLK
Note: For additional margin testing frequencies, refer to Byte 4
0489C--12/10/04
Integrated Circuit Systems, Inc.
ICS952004
General Description
The ICS952004 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952004 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER 1, 11, 13, 19, 29, 42, 48 2 3 4 5, 8, 18, 24, 25, 32, 37, 41, 46 6 7 10, 9 12 14 15 23, 22, 21, 20, 17, 16 26 27 28, 36 30, 31 PIN NAME VDD FS0 TYPE PWR IN Power supply for 3.3V Frequency select pin. 14.318 MHz reference clock. Frequency select pin. 14.318 MHz reference clock. Frequency select pin. 14.318 MHz reference clock. Ground pin for 3V outputs. Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Hyperzip clock outputs. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when MODE pin is in Mobile mode Frequency select pin. PCI clock output, not affected by PCI_STOP# Frequency select pin. PCI clock output, not affected by PCI_STOP# PCI clock outputs. 3.3V LVTTL input for selecting the current multiplier for CPU outputs. Clock output for super I/O/USB default is 24MHz 48MHz output clock Analog power supply 3.3V AGP outputs defined as 2X PCI. These may not be stopped. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD goes high the frequency select will be latched at power on thereafter the pin is an asynchronous active low power down pin. 2 Data pin for I C circuitry 5V tolerant 2 Clock pin of I C circuitry 5V tolerant DESCRIPTION
REF0
FS1
OUT
IN
REF1
FS2
OUT
IN
REF2
GND X1 X2 ZCLK(1:0) PCI_STOP# FS3 PCICLK_F0 FS4 PCICLK_F1 PCICLK (5:0) MULTISEL 24_48MHz 48MHz AVDD AGPCLK (1:0) PD#
OUT
PWR IN OUT OUT IN IN OUT IN OUT OUT IN OUT OUT PWR OUT IN
33 Vtt_PWRGD 34 35 38 SDATA SCLK IN I/O IN
I REF
OUT
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current.
"Complementary" clocks of differential pair CPU outputs. These clocks are 180 out of phase with SDRAM clocks. These open drain outputs need an external 1.5V pull-up. "True" clocks of differential pair CPU outputs. These clocks are in phase with SDRAM clocks. These open drain outputs need an external 1.5V pullup. Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile mode SDRAM clock output.
43, 39
CPUCLKC (1:0)
OUT
44, 40 45 47
CPUCLKT (1:0) CPU_STOP# SDRAM
OUT IN OUT
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Integrated Circuit Systems, Inc.
ICS952004
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 Byte 23 Bit 7 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.56V @ 60 0.47V @ 50 0.85V /2 60 0.71V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.60 @ 20 0.5V @ 20 0.90V @ 30 0.75V @ 20 1.05V @ 30 0.84V @ 20
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Integrated Circuit Systems, Inc.
ICS952004
General I2C serial interface information for the ICS952004 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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Integrated Circuit Systems, Inc.
ICS952004
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer. Byte4: Functionality and Frequency Select Register (default = 0)
Bit Description Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK 66.67 0 0 0 0 0 66.67 66.67 0 0 0 0 1 100.00 100.00 66.67 0 0 0 1 0 100.00 200.00 66.67 0 0 0 1 1 100.00 133.33 66.67 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 100.00 160.00 66.67 0 0 1 1 1 100.00 133.33 80.00 0 1 0 0 0 100.00 200.00 66.67 62.50 0 1 0 0 1 100.00 166.67 0 1 0 1 0 100.00 166.67 71.43 0 1 0 1 1 0 1 1 0 0 63.33 0 1 1 0 1 95.00 95.00 0 1 1 1 0 95.00 126.67 63.33 0 1 1 1 1 1 0 0 0 0 105.00 140.00 70.00 1 0 0 0 1 100.90 100.90 67.27 1 0 0 1 0 108.00 144.00 72.00 1 0 0 1 1 100.90 134.53 67.27 1 0 1 0 0 112.00 149.33 74.67 66.67 1 0 1 0 1 133.33 100.00 1 0 1 1 0 133.33 133.33 66.67 1 0 1 1 1 133.33 166.67 66.67 1 1 0 0 0 100.00 133.00 80.00 1 1 0 0 1 100.00 100.00 80.00 166.67 83.33 1 1 0 1 0 100.00 1 1 0 1 1 1 1 1 0 0 100.00 133.00 100.00 100.00 1 1 1 0 1 100.00 100.00 1 1 1 1 0 100.00 166.67 100.00 1 1 1 1 1 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit , 2 7:4 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD AGP PCI 66.67 33.33 66.67 33.33 66.67 33.33 66.67 33.33 (Reserved) (Reserved) 66.67 33.33 66.67 33.33 66.67 33.33 62.50 31.25 83.33 41.67 (Reserved) (Reserved) 63.33 31.67 63.33 31.67 ( R e s e r ve d ) 35.00 70.00 67.27 33.63 72.00 36.00 67.27 33.63 74.67 37.33 66.67 33.33 66.67 33.33 66.67 33.33 66.67 33.33 66.67 33.33 62.50 31.25 (Reserved) 66.67 33.33 66.67 33.33 62.50 31.25 (Reserved) Spread Precentage 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread
+/- 0.25% Center Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread
Bit 2 Bit 7:4
+/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread
00000 Note1
Bit 3 Bit 1 Bit 0
0 0 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. Note: PWD = Power-Up Default
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Integrated Circuit Systems, Inc.
Byte 5: Control Register (1 = enable, 0 = disable)
ICS952004
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 30 31 26 15 14 4 3 2
PWD 1 1 0 X X X X X
Description AGPCLK1 AGPCLK1 SEL24_48MHz (0=24MHz, 1=48MHz) FS4 Read Back FS3 Read Back FS2 Read Back FS1 Read Back FS0 Read Back
Byte 6: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 10 9 14 15 40, 39 44, 43 39, 40 43, 44
PWD 1 1 0 0 1 1 1 1
Description ZCLK1 ZCLK0 PCICLK_F0 stop control 0 = Free Running; 1 = Stop PCICLK_F1 stop control 0 = Free Running; 1 = Stop CPUCLKT/C0 stop control 0 = Free Running; 1 = Stop CPUCLKT/C1 stop control 0 = Free Running; 1 = Stop CPUCLKT/C0 output control CPUCLKT/C1 output control
Byte 7: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 15 14 23 22 21 20 17 16
PWD 1 1 1 1 1 1 1 1
Description PCICLK_F1 PCICLK_F0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 8: Byte Count Read Back Register
Bit Bit 7 Bi t 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bi t 1 Bi t 0
Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure 0 byte count and how many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS952004
Byte 9: Watchdog Timer Count Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to X * 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16 * 290ms = 4.6 seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bit 7
Name Program Enable
PWD 0 0 0 0 0 0 0 1
Bit 6 WD Enable Bit 5 WD Alarm Bit 4 S F4 Bit 3 SF3 Bit 2 SF2 Bit 1 SF1 Bit 0 SF0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2 C programing. Watchdog Enable bit Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8 The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD X X X X X X X X
Description The decimal representation of Ndiv (8:0) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
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Integrated Circuit Systems, Inc.
ICS952004
Byte 13: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD X X X X X X X X
Description The Spread Spectrum (12:0) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bit 1 B it 0
Name SD Div 3 SD Div 2 SD Div 1 SD Div 0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD X X X X X X X X
Description SDRAM clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPUCLKT/C clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bi t 6 Bi t 5 Bi t 4 Bit 3 Bi t 2 Bit 1 Bi t 0
Name AGP Div 3 AGP Div 2 AGP Div 1 AGP Div 0 ZCLK Div 3 ZCLK Div 2 ZCLK Div 1 ZCLK Div 0
PWD X X X X X X X X
Description AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. ZCLK clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
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Integrated Circuit Systems, Inc.
ICS952004
Byte 17: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
Name AGP_INV ZCLK_INV SD_INV CPU_INV PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0
PWD 0 0 0 0 X X X X
Description AGP Phase Inversion bit ZCLK Phase Inversion bit SDRAM Phase Inversion bit CPUCLK Phase Inversion bit PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to table 2. Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2) Div (1:0) 00 01 10 11
00 /2 /3 /5 /7
01 /4 /6 /10 /14
10 /8 /12 /20 /28
11 /16 /24 /40 /56
Div (3:2) Div (1:0) 00 01 10 11
00 /4 /3 /5 /7
01 /8 /6 /10 /14
10 /16 /12 /20 /28
11 /32 /24 /40 /56
Byte 18: Group Skew Control Register
Bit Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 B it 0
Name CPU_Skew 1 CPU_Skew 0 SD_Skew 1 SD_Skew 0 (Reser ved) (Reser ved) (Reser ved) Async 3V66
PWD 1 1 0 0 X 0 0 0
Description These 2 bits delay the CPUCLKT/C (1:0) clocks with respect to all other clocks. 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps These 2 bits delay the SDRAM with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps (Reser ved) (Reser ved) (Reser ved) 0 = 3V66 sync to CPUCLK 1 = 3V66 async to CPUCLK = 66.00 MHz
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Integrated Circuit Systems, Inc.
ICS952004
Byte 19: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name These 4bits control CPU-ZCLK(1:0)
PWD 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Programmable Delay Stop 0 0 1 1 0 0 0 1 0 1 0 1 1.85ns 2.00ns 2.15ns 2.30ns 2.45ns 2.60ns 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 3.05ns 3.20ns 3.35ns 3.50ns 3.65ns 3.80ns
These 4 bits control CPU-AGP(1:0)
0 1 1 0 2.75ns 1 1 1 0 3.95ns 0 1 1 1 2.90ns 1 1 1 1 4.10ns
Byte 20: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name These 4bits control CPU-PCICLK_F(1:0)
PWD 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Programmable Delay Stop 0 0 1 1 0 0 0 1 0 1 0 1 1.85ns 2.00ns 2.15ns 2.30ns 2.45ns 2.60ns 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 3.05ns 3.20ns 3.35ns 3.50ns 3.65ns 3.80ns
These 4 bits control CPU-PCICLK(5:0)
0 1 1 0 2.75ns 1 1 1 0 3.95ns 0 1 1 1 2.90ns 1 1 1 1 4.10ns
Byte 21: Slew Rate Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0
Name 24/48_Slew AGP_Slew ZCLK_Slew REF_Slew
PWD 0 0 0 0 0 0 0 0
Description 24/48 MHz clock slew rate control bits. 01 = strong; 00, 11 = normal; 10 = weak AGP clock slew rate control bits. 01 = strong; 00, 11 = normal; 10 = weak ZCLK clock slew rate control bits. 01 = strong; 00, 11 = normal; 10 = weak REF clock slew rate control bits. 01 = strong; 00, 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SDRAM Slew (Reser ved) PCICLK_F Slew PCICLK Slew
PWD 0 0 X X 0 0 0 0
Description SDRAM clock slew rate control bits. 01 = strong; 00, 11 = normal;10 = weak (Reser ved) PCICLK_F clock slew rate control bits. 01 = strong; 00, 11 = normal;10 = weak PCICLK clock slew rate control bits. 01 = strong; 00, 11 = normal;10 = weak
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Integrated Circuit Systems, Inc.
ICS952004
Byte 23: Output Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 47 27 26 4 3 2
PWD 0 1 1 1 1 1 1 1
Description Iref Output Control MULITSEL Readback SDRAM 48MHz 24_48MHz REF2 REF1 REF0
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Integrated Circuit Systems, Inc.
ICS952004
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization
1
CONDITIONS
MIN 2 VSS-0.3
TYP
MAX VDD+0.3 0.8 5
UNITS V V mA mA
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = Full load IREF=2.32 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs)
-5 -5 -200 215 16 14.318
IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX TSTAB
280 25 7 5 6 45
mA mA MHz nH pF pF pF ms ns ns ns
27 1.3 0.4
1,2
1.8 1 10 10
CPU to SDRAM SKEW tPZH,tPZL Delay
1 2 1
1 1
tPHZ,tPLZ
Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements.
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Integrated Circuit Systems, Inc.
ICS952004
Electrical Characteristics - CPU (0.7V Select)
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 2pF (unless otherwise specified) PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle
1 2
SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross tr tf d-tr d-tf dt3 tsk3 tjcyc-cyc1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -450 250
TYP
MAX UNITS
773 38 788 -2 342 28
850 150 1150 550 140 700 700 125 125 55 100 150 mV mV mV mV ps ps ps ps % ps ps
175 175
314 396 15 46 51 23 57
Measurement from differential wavefrom VT = 50% VT = 50%
45
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V, 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V, 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 Jitter
1
MIN 12 2.4 -66 60 0.5 0.5 45
TYP 3.25 0.05 -130 -15 145 59 0.65 0.61 46 172
MAX 55 0.55 -33 72 2 2 55 200
UNITS V V mA mA ns ns % ps
tjcyc-cyc
1
VT = 1.5 V 3V66
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
Integrated Circuit Systems, Inc.
ICS952004
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS FO1 Output Frequency 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V, 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V, 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 1 VT = 1.5 V Skew tsk1 1 VT = 1.5 V Jitter,cycle to cyc tjcyc-cyc
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33 3.25 0.05 -58 -7 62 23 1.89 1.85 51.8 194 250
MAX 55 0.55 -33 38 2 2 55 500 500
UNITS MHz V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24_48MHz, 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS FO1 Output Frequency 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL VOH@MIN = 1.0 V, 1 VOH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V 48MHz Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V 48MHz Fall Time tf1 1 VT = 1.5 V 48MHz Duty Cycle dt1 1 VT = 1.5 V 48MHz Jitter tjcyc-cyc
1
MIN 20 2.4 -29 29 1 1 45
TYP 48 3.25 0.05 -58 -7 62 23 1.27 1.36 54.5 287
MAX 60 0.4 -23 27 2 2 55 350
UNITS MHz V V mA mA ns ns % ps
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
14
Integrated Circuit Systems, Inc.
ICS952004
Electrical Characteristics - ZCLK [1:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS FO1 Output Frequency 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL VOH@MIN = 1.0 V, 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V, 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 Skew Jitter
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.67 3.25 0.05 -72 -9 78 29 1.6 1.4 51.8 24 400
MAX 55 0.55 -33 38 2 2 55 150 500
UNITS MHz V V mA mA ns ns % ps ps
tsk1
1
VT = 1.5 V VT = 1.5 V
1 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP [1:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS FO1 Output Frequency 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL VOH@MIN = 1.0 V, 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V, 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL @MAX = 0.4 V Output Low Current IOL 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 Skew Jitter
1
MIN 12 2.4 -33 30
TYP 66.67 3.25 0.05 -72 -9 78 29 1.86 1.49 51 6 379
MAX 55 0.55 -33 38 38 2 2 55 250 400
UNITS MHz V V mA mA mA ns ns % ps ps
0.5 0.5 45
tsk1
1
VT = 1.5 V VT = 1.5 V 3V66
1 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
15
Integrated Circuit Systems, Inc.
ICS952004
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS FO1 Output Frequency 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V, 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V, 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 Jitter
1
MIN 20 2.4 -33 30 1 1 45
TYP 14.3 3.25 0.05 -58 -7 62 23 1.4 1.3 54.3 312
MAX 60 0.55 -33 38 4 4 55 1000
UNITS MHz V V mA mA ns ns % ps
tjcyc-cyc
1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
16
Integrated Circuit Systems, Inc.
ICS952004
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
17
Integrated Circuit Systems, Inc.
ICS952004
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F 33MHz PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_ST OP # CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
Third party brands and names are the property of their respective owners.
18
Integrated Circuit Systems, Inc.
ICS952004
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
Ordering Information
ICS952004yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
19

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